Data bus efficiency via cache line usurpation

专利名称：Data bus efficiency via cache line usurpation发明人：Steven Gerard LeMire,Vuong Cao Nguyen申请号：US14517555申请日：20141017公开号：US09043558B2公开日：20150526

专利附图：

摘要：Embodiments of the current invention permit a user to allocate cache memoryto main memory more efficiently. The processor or a user allocates the cache memoryand associates the cache memory to the main memory location, but suppresses orbypassing reading the main memory data into the cache memory. Some embodiments of

the present invention permit the user to specify how many cache lines are allocated at agiven time. Further, embodiments of the present invention may initialize the cachememory to a specified pattern. The cache memory may be zeroed or set to some desiredpattern, such as all ones. Alternatively, a user may determine the initialization patternthrough the processor.

申请人：Emulex Corporation

地址：Costa Mesa CA US

国籍：US

代理机构：McAndrews, Held & Malloy Ltd.

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