Frequency dividing circuit capable of varying divi

专利名称：Frequency dividing circuit capable of varying

dividing ratio

发明人：Kazuo Yamashita申请号：US07/598177申请日：19901015公开号：US050777A公开日：19911231

摘要：A frequency dividing circuit divides an input signal of an input frequency into anoutput signal of an output frequency. The frequency dividing circuit comprises firstthrough fourth latch circuits which operate the input signal, respectively. The first latchcircuit delays an original signal into a first delay signal. The second latch circuit delays thefirst delay signal to produce a second delay signal and a first inverted delay signal whichhas an antiphase relative to the second delay signal. The third latch circuit delays thesecond delay signal into a third delay signal as the output signal. The fourth latch circuitreceives a first OR signal which is produced by logically adding the third delay signal andmode signal which has first and second levels. The fourth latch signal delays the first ORsignal into a fourth delay signal and produces a second inverted delay signal which has anantiphase relative to the fourth delay signal. The first latch circuit receives a second ORsignal as the original signal which is produced by logically adding the first and the secondinverted delay signals. The output frequency of the output signal has a first frequencywhen the mode signal has the first level and has a second frequency which is differentfrom the first frequency when the mode signal has the second level.

申请人：JAPAN RADIO CO., LTD.

代理机构：Frishauf, Holtz, Goodman & Woodward

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