MT46H64M16LFBF-5 IT_B

Prior to normal operation, the device must be powered up and initialized in a prede-fined manner. Using initialization procedures other than those specified will result inundefined operation.

If there is an interruption to the device power, the device must be re-initialized usingthe initialization sequence described below to ensure proper functionality of the device.To properly initialize the device, this sequence must be followed:

1.The core power (VDD) and I/O power (VDDQ) must be brought up simultaneously.It is recommended that VDD and VDDQ be from the same power source, or VDDQmust never exceed VDD. Standard initialization requires that CKE be assertedHIGH (see Figure 17 (page 54)). Alternatively, initialization can be completedwith CKE LOW provided that CKE transitions HIGH tIS prior to T0 (see Figure 18(page 55)).

2.When power supply voltages are stable and the CKE has been driven HIGH, it issafe to apply the clock.

3.When the clock is stable, a 200μs minimum delay is required by the Mobile LPDDRprior to applying an executable command. During this time, NOP or DESELECTcommands must be issued on the command bus.4.Issue a PRECHARGE ALL command.

5.Issue NOP or DESELECT commands for at least tRP time.

6.Issue an AUTO REFRESH command followed by NOP or DESELECT commandsfor at least tRFC time. Issue a second AUTO REFRESH command followed by NOPor DESELECT commands for at least tRFC time. Two AUTO REFRESH commandsmust be issued. Typically, both of these commands are issued at this stage as de-scribed above.

7.Using the LOAD MODE REGISTER command, load the standard mode register asdesired.

8.Issue NOP or DESELECT commands for at least tMRD time.

9.Using the LOAD MODE REGISTER command, load the extended mode register tothe desired operating modes. Note that the sequence in which the standard andextended mode registers are programmed is not critical.10.Issue NOP or DESELECT commands for at least tMRD time.

After steps 1–10 are completed, the device has been properly initialized and is ready toreceive any valid command.

质量等级领域:宇航级IC、特军级IC、超军级IC、普军级IC、禁运IC、工业级IC，军级二三极管，功率管等;

应用领域:航空航天、船舶、汽车电子、军用计算机、铁路、医疗电子、通信网络、电力工业以及大型工业设备祝您:工作顺利，生活愉快!

以深圳市美光存储技术有限公司提供的参数为例，以下为MT46H64M16LFBF-5 IT_B的详细参数，仅供参考

1Gb: x16, x32 Mobile LPDDR SDRAM

Standard Mode Register

Standard Mode Register

The standard mode register bit definition enables the selection of burst length, bursttype, CAS latency (CL), and operating mode, as shown in Figure 19. Reserved statesshould not be used as this may result in setting the device into an unknown state orcause incompatibility with future versions of LPDDR devices. The standard mode regis-ter is programmed via the LOAD MODE REGISTER command (with BA0 = 0 and BA1 =0)and will retain the stored information until it is programmed again, until the devicegoes into deep power-down mode, or until the device loses power.

Reprogramming the mode register will not alter the contents of the memory, provided itis performed correctly. The mode register must be loaded when all banks are idle andno bursts are in progress, and the controller must wait tMRD before initiating the subse-quent operation. Violating any of these requirements will result in unspecified opera-tion.

Figure 19: Standard Mode Register Definition

BA1BA0An...A10A9A8A7A6A5A4A3A2A1A0Address busn + 2n + 1n...1098Operating Mode0076543210CAS LatencyBTBurst LengthStandard mode register (Mx) Mn + 2 Mode Register DefinitionMn + 100110101Standard mode registerStatus registerExtended mode registerReservedM2M1M000001Mn ...M10 M9 M8 M7Operating Mode 0–0–0–0–0–Normal operationAll other states reservedM6M5M4000011110011001101010101CAS LatencyReservedReserved23ReservedReservedReservedReservedM3 011110011001101010101Burst LengthM3 = 0Reserved24816ReservedReservedReservedM3 = 1Reserved24816ReservedReservedReservedBurst Type SequentialInterleavedNote:1.The integer n is equal to the most significant address bit.

1Gb: x16, x32 Mobile LPDDR SDRAM

Extended Mode Register

Extended Mode Register

The EMR controls additional functions beyond those set by the mode registers. Theseadditional functions include drive strength, TCSR, and PASR.

The EMR is programmed via the LOAD MODE REGISTER command with BA0 = 0 andBA1 = 1. Information in the EMR will be retained until it is programmed again, the de-vice goes into deep power-down mode, or the device loses power.

Figure 21: Extended Mode Register

BA1BA0An...A10A9A8A7A6A5A4A3A2A1A0Address busn + 2n + 1n109...10Operation876DS5431 TCSR21PASR0Extended moderegister (Ex)En + 2En + 1Mode Register Definition00Standard mode register01Status register10Extended mode register11ReservedE700001111E600110011E501010101Drive StrengthFull strength1/2 strength1/4 strength3/4 strength 3/4 strengthReservedReservedReservedE200001111E100110011E001010101Partial-Array Self Refresh CoverageFull array1/2 array1/4 arrayReservedReserved1/8 array1/16 arrayReservedEn0–...0–E10E90–0–E80–E7–E0Valid–Normal AR operationAll other states reservedNotes:

1.On-die temperature sensor is used in place of TCSR. Setting these bits will have no ef-fect.

2.The integer n is equal to the most significant address bit.

Temperature-Compensated Self Refresh

This device includes a temperature sensor that is implemented for automatic control ofthe self refresh oscillator. Programming the temperature-compensated self refresh(TCSR) bits will have no effect on the device. The self refresh oscillator will continue torefresh at the optimal factory-programmed rate for the device temperature.

1Gb: x16, x32 Mobile LPDDR SDRAM

Extended Mode Register

Partial-Array Self Refresh

For further power savings during self refresh, the partial-array self refresh (PASR) featureenables the controller to select the amount of memory to be refreshed during self re-fresh. The refresh options include:

1Gb: x16, x32 Mobile LPDDR SDRAM

Bank/Row Activation

Bank/Row Activation