BS62LV8001EIG55资料

Very Low Power/Voltage CMOS SRAM1M X 8 bitBS62LV8001•Wide Vccoperation voltage : 2.4V ~ 5.5V •Very low power consumption :

Vcc= 3.0V C-grade: 30mA (@55ns) operating current

I -grade:31mA (@55ns) operating currentC-grade: 24mA (@70ns) operating currentI -grade:25mA (@70ns) operating current1.5uA (Typ.)CMOS standby current

Vcc= 5.0V C-grade: 75mA (@55ns) operating current

I -grade:76mA (@55ns) operating currentC-grade: 60mA (@70ns) operating currentI -grade:61mA (@70ns) operating current8.0uA (Typ.)CMOS standby current

•High speed access time :

-55 55ns -70 70ns

•Automatic power down when chip is deselected

•Three state outputs and TTL compatible•Fully static operation

•Data retention supply voltage as low as 1.5V•Easy expansion with CE1, CE2 and OE options󰂄GENERAL DESCRIPTION

The BS62LV8001 is ahigh performance , very low power CMOS Static Random Access Memory organized as 1,048,576 wordsby 8 bits and operates from a wide range of 2.4V to 5.5V supply voltage.

Advanced CMOS technology and circuit techniques provide bothhighspeed and low power features with a typical CMOS standby current of1.5uAat 3V/25oC and maximum access time of 55ns at 3.0V/85oC.

Easy memory expansion is provided by an active LOW chip enable(CE1), an active HIGH chip enable (CE2) and active LOW output enable (OE) and three-state output drivers.

The BS62LV8001 hasanautomatic power down feature, reducing thepower consumption significantly when chip is deselected.

The BS62LV8001 is available in 48B BGA and 44L TSOP2 packages.

󰂄PRODUCT FAMILYPRODUCTFAMILYBS62LV8001ECBS62LV8001FCBS62LV8001EIBS62LV8001FIOPERATINGTEMPERATURE+0O C to +70O C-40O C to +85O CVccRANGE2.4V ~ 5.5V2.4V ~ 5.5VSPEED( ns )55ns : 3.0~5.5V70ns : 2.7~5.5V( ICCSB1, Max )POWER DISSIPATIONSTANDBYOperating( ICC, Max )PKG TYPETSOP2-44BGA-48-0912TSOP2-44BGA-48-0912Vcc=3VVcc=5VVcc=3V70nsVcc=5V70ns55 / 7055 / 705uA10uA55uA110uA24mA25mA60mA61mA󰂄PIN CONFIGURATIONS

A4A3A2A1A0CE1NCNCDQ0DQ1VCCGNDDQ2DQ3NCNCWEA19A18A17A16A15123456789101112131415161718192021221

444342414039383736353433323130292827262524235

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A5A6A7OECE2A8NCNCDQ7DQ6GNDVCCDQ5DQ4NCNCA9A10A11A12A13A14󰂄FUNCTIONAL BLOCK DIAGRAM

BS62LV8001ECBS62LV8001EIA13A17A15A18A16A14A12A7A6A5A4AddressInputBuffer22RowDecoder2048Memory Array2048X 40964096DQ0DQ1DQ2DQ3DQ4DQ5DQ6DQ7CE1CE2WEOEVddGnd8DataInputBuffer8Column I/OWrite DriverSense Amp8512Column Decoder18ControlAddress Input Buffer234

ANCOEA0A1A2CE2

BNCNCA3A4CE1NC

NC8CD0NCA5A6

DataOutputBufferD4

DVSSD1A17A7D5VCC

E

VCCD3

D2VCCA16D6VSS

FNCA14A15NCD7

A11A9 A8 A3 A2 A1 A0A10 A19GNCNCA12A13WENC

HA18A8A9A10A11A19

48-ball BGA top view

Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.

R0201-BS62LV8001

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BSI󰂄PIN DESCRIPTIONS

BS62LV8001FunctionThese 20address inputsselect one of the 1,048,576x 8-bit wordsin the RAMCE1 is active LOW and CE2 is active HIGH. Both chip enables mustbe active whendata read from or write to the device. If either chip enable is not active, the device isdeselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected. The write enable input is active LOW and controls read and writeoperations. With thechip selected, when WE is HIGH and OE is LOW, output data will be present on theDQ pins; when WE is LOW, the data present on the DQ pins will bewritten into theselected memory location.NameA0-A19 Address InputCE1 Chip Enable 1 InputCE2 Chip Enable 2 InputWE Write Enable InputOE Output Enable InputThe output enable input is active LOW. If the output enable is active while the chip isselected and the write enable is inactive, data will be present on the DQ pins and theywill be enabled. The DQ pins will be in the high impedance statewhen OE is inactive.DQ0-DQ7 Data Input/OutputPortsVccGndThese 8 bi-directional ports are used to read data from or write data into the RAM.Power SupplyGround󰂄TRUTH TABLE

MODENot selected(Power Down)Output DisabledReadWriteWEXXHHLCE1HXLLLCE2XLHHHOEXXHLXI/O OPERATIONHigh ZHigh ZDOUTDINVccCURRENTICCSB, ICCSB1ICCICCICC󰂄ABSOLUTE MAXIMUM RATINGS(1)

SYMBOLVTERMTBIASTSTGPTIOUTPARAMETERTerminal Voltage withRespect to GNDTemperature Under BiasStorage TemperaturePower DissipationDC Output Current󰂄OPERATING RANGE

UNITSVO RATING-0.5 toVcc+0.5-40 to +85-60 to +1501.020RANGECommercialIndustrialAMBIENTTEMPERATURE0 O C to +70 O C-40 O C to +85 O CVcc2.4V~5.5V2.4V~5.5VCCO WmA󰂄CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)

SYMBOLPARAMETERInputCapacitanceInput/OutputCapacitanceCONDITIONSMAX.UNIT1. Stresses greater than those listed under ABSOLUTE MAXIMUM

CINVIN=0V10RATINGS may cause permanent damage to the device. This is astress rating only and functional operation of the device at theseCDQVI/O=0V12or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure toabsolute

1. This parameter is guaranteed and not 100% tested.

maximum rating conditions for extended periods may affectreliability.

pFpFR0201-BS62LV8001

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BSI󰂄DC ELECTRICAL CHARACTERISTICS ( TA = -40oC to + 85oC )PARAMETER NAME VIL VIH IIL ILO VOL VOH ICC (4)BS62LV8001TEST CONDITIONS Vcc = Max, VIN = 0V to Vcc Vcc = Max, CE1 = VIH or CE2 = VIL or OE = VIH, VI/O = 0V to Vcc Vcc = Max, IOL = 2mA Vcc = Min, IOH = -1mA Vcc=3V Vcc=5V Vcc=3V Vcc=5V 70ns Vcc3V 70ns Vcc5V Vcc=3V Vcc=5V Vcc=3V Vcc=5V Vcc=3V Vcc=5V Vcc=3V Vcc=5V PARAMETER Guaranteed Input Low Voltage(3) Guaranteed Input High Voltage(3) Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage MIN. TYP. (1) MAX. UNITS-0.5 -- 0.8 V -0.5 -- 0.8 2.0 -- Vcc+0.3V 2.2 -- Vcc+0.3-- -- 1 uA -- -- 1 uA -- -- 0.4 V 2.4 -- -- V -- -- 25 mA -- -- 61 -- -- 1 mA -- -- 2 -- 1.5 10 uA -- 8.0 110 Operating Power Supply CE1= VIL, CE2= VIH, IDQ = 0mA, F = Fmax(2) Current ICCSB Standby Current-TTL CE1 VIH or CE2= VIL, IDQ = 0mAICCSB1 Standby Current-CMOS (5)CE1≧Vcc-0.2V or CE2≦0.2V VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V 1. Typical characteristics are at TA = 25oC. 2. Fmax= 1/tRC.

3. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 4. Icc_Max.is 31mA(@3.0V)/76mA(@5.0V) under 55ns operation. 5.IccsB1is 5uA/55uAatVcc=3.0V/5.0V and TA=70oC.

󰂄DATA RETENTION CHARACTERISTICS ( TA = -40 to + 85oC )

SYMBOL VDR PARAMETER Vcc for Data Retention TEST CONDITIONS =CE1≧ Vcc - 0.2V or CE2 ≦ 0.2V, VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V CE1≧ Vcc - 0.2V or CE2 ≦ 0.2V, VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V ==MIN. TYP. (1) MAX. 1.5 -- -- UNITS V ICCDR(3) tCDR tR Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time -- 0.8 2.5 uA ns ns 0 -- -- See Retention Waveform TRC (2)-- -- 1. Vcc = 1.5V,TA= + 25OC 2.tRC= Read Cycle Time

O3.IccDR(Max.) is 1.3uAat TA=70C.

󰂄LOW VCCDATA RETENTION WAVEFORM (1) ( CE1 Controlled )

Data Retention Mode

Vcc

VIH

Vcc

VDR≥1.5V

Vcc

tCDR

≥CE1 Vcc -0.2V

tR

VIH

CE1󰂄LOW VCCDATA RETENTION WAVEFORM (2) ( CE2 Controlled )

Data Retention Mode

VDR≧1.5V

Vcc

VccVcc

tCDR

tR

CE2 ≦0.2V

CE2

VILVIL

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BSI󰂄AC TEST CONDITIONS

(Test Load and Input/Output Reference)

BS62LV8001󰂄KEY TO SWITCHING WAVEFORMS

Vcc / 0V 1V/ns 0.5Vcc CL = 30pF+1TTL CL = 100pF+1TTL WAVEFORMINPUTSMUST BESTEADYMAY CHANGEFROM H TO LMAY CHANGEFROM L TO HDON T CARE:ANY CHANGEPERMITTEDDOES NOTAPPLYOUTPUTSMUST BESTEADYWILL BECHANGEFROM H TO LWILL BECHANGEFROM L TO HCHANGE :STATEUNKNOWNCENTERLINE IS HIGHIMPEDANCE”OFF ”STATEInput Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load ,

󰂄AC ELECTRICAL CHARACTERISTICS ( TA = -40oC to + 85oC )

READ CYCLEJEDECPARAMETERNAMEPARAMETERNAMECYCLE TIME : 70nsCYCLE TIME : 55nsVcc=3.0~5.5VDESCRIPTIONRead Cycle TimeAddress Access TimeChip Select Access Time (CE1)Chip Select Access Time (CE2)Output Enable to Output ValidChip Select to Output Low ZOutput Enable to Output in Low ZChip Deselect to Output in High ZOutput Disable to Output in High ZData Hold from Address Change Vcc=2.7~5.5VMIN. TYP. MAX.MIN. TYP. MAX.UNITnsnsnsnsnsnsnsnsnsnstAVAXtAVQVtE1LQVtE2LQVtGLQVtELQXtGLQXtEHQZtGHQZtAXOXtRCtAAtACS1tACS2tOEtCLZtOLZtCHZtOHZtOH70--------1010----10----------------------70707035----3530--55--------1010----10----------------------55555530----3025--R0201-BS62LV8001

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BSI󰂄SWITCHING WAVEFORMS (READ CYCLE)

READ CYCLE1

(1,2,4)

BS62LV8001t RC

ADDRESS

t OH

DOUT

t AA

t OH

READ CYCLE2 (1,3,4)

CE2ttACS2ACS1CE1tD OUT(5)CLZt(5)CHZREAD CYCLE3 (1,4)ADDRESSt RCtOEAAtCE2OEtOHtttt(5)CLZACS2CE1OLZACS1ttOHZCHZ(5)(1,5)D OUTNOTES:

1. WE is high in read Cycle.

2. Device is continuously selected when CE1 = VIL and CE2 = VIH.

3. Address valid prior to or coincident with CE1 transition low and CE2 transition high.4. OE =VIL.

5. The parameter is guaranteed but not 100% tested.

R0201-BS62LV8001

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BSI󰂄AC ELECTRICAL CHARACTERISTICS ( TA = -40oC to + 85oC )

WRITE CYCLE

JEDECPARAMETERNAMEPARAMETERNAMECYCLE TIME : 70nsBS62LV8001CYCLE TIME : 55ns(Vcc=3.0~5.5V)DESCRIPTIONWrite Cycle TimeChip Select to End of WriteAddress Set up TimeAddress Valid to End of WriteWrite Pulse WidthWrite Recovery Time (CE2,CE1 , WE)Write to Output in High ZData to Write Time OverlapData Hold from Write TimeOutput Disable to Output in High ZEnd of Write to Output Active(Vcc=2.7~5.5V)MIN. TYP. MAX.MIN. TYP. MAX.UNITtAVAXtE1LWHtAVWLtAVWHtWLWHtWHAXtWLOZtDVWHtWHDXtGHOZtWHQXtWCtCWtAStAWtWPtWRtWHZtDWtDHtOHZtOW7070070350--300--5----------------------------------30----30--5555055300--250--5----------------------------------25----25--nsnsnsnsnsnsnsnsnsnsns󰂄SWITCHING WAVEFORMS (WRITE CYCLE)WRITE CYCLE1(1)ADDRESStWCt WROE(3)CE2(5)t CW(5)(11)CE1tAWWE(3)t AS(4,10)t WP(2)t OHZD OUTt DHt DWDINR0201-BS62LV8001

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BSIWRITE CYCLE2(1,6)

BS62LV8001t WCADDRESSCE2(11)CE1(5)tCWtWEAWtWPtWR(3)(2)t AS(4,10)t WHZD OUTt OWtDWt DH(8,9)(7)(8)DINNOTES:

1. WE must be high during address transitions.

2. The internal write time of the memory is defined by the overlap of CE2, CE1 and WE low. All signalsmust be active to initiate a write and any one signal can terminate a write by going inactive.The data input setup and hold timing should be referenced to the second transition edge ofthe signal that terminates the write.

3. TWRis measured from the earlier of CE2 going low, or CE1 or WE going high at the end of write cycle.4. During this period, DQ pins are in the output state so that the input signals of opposite phaseto the outputs must not be applied.

5. If the CE2 high transition or CE1 low transition occurs simultaneously with the WE low transitions or after the WEtransition, output remain in a high impedance state.6. OE is continuously low (OE =VIL).

7.DOUTis the same phase of write data of this write cycle.8.DOUTis the read data of next address.

9. If CE2 is high or CE1 is low during this period, DQ pins are in the output state. Then the data input signals ofopposite phase to the outputs must not be applied to them.10. The parameter is guaranteed but not 100% tested.

11.TCW is measured from the later of CE2 going high or CE1 going low tothe end of write.

R0201-BS62LV8001

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BSI󰂄ORDERING INFORMATION

BS62LV8001BS62LV8001 X XZY YSPEED55: 55ns70: 70nsPKG MATERIAL-: NormalG: GreenP:Pb freeGRADEC: +0oC ~ +70oCI: -40oC ~ +85oCPACKAGEE: TSOP2-44F: BGA-48-0912Note:

BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its productsfor use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-supportsystems and critical medical instruments.

󰂄PACKAGE DIMENSIONS

TSOP2-44

R0201-BS62LV8001

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BSI󰂄PACKAGE DIMENSIONS (continued)

0.25±0.051.4 Max.BS62LV8001NOTES:1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. 3: SYMBOL \"N\" IS THE NUMBER OF SOLDER BALLS.SIDE VIEWD0.13.375D1N ED4812.09.0D15.25E13.75e0.75SOLDER BALL 0.35±0.05eVIEW A48 mini-BGA (9mm x 12mm)

2.625E±0.1E1R0201-BS62LV8001

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