L-LCK4802资料

December2001

LCK4802

Low-VoltagePECLDifferentialClock

General

TheLCK4802isalow-voltage,3.3VPECL

differentialclocksynthesizer.TheLCK4802supportstwodifferentialPECLoutputpairswithfrequenciesfrom336MHzto1GHz.TheclockisdesignedtosupportsingleandmultipleprocessorsystemsthatrequirePECLdifferentialinputs.TheLCK4802containsafullyintegratedPLL(phase-lockedloop)whichmultipliesthePECL_CLKinputfrequencytomatchindividualprocessorclockfrequencies.ThePLLcanbebypassedsothatthePCLKoutputsarefedfromthePECL_CLKorPECL_CLKinputfortestpurposes.Alloutputsarepoweredfroma2Vexternalsupplytoreduceon-chippower

consumption.AlloutputsarePECL.ThePLLcanoperateintheinternalfeedbackmode,orintheexternalfeedbackmodeforboardleveldebuggingapplications.

Features

sssssss

Twofullyselectableclockinputs.FullyintegratedPLL.

336MHzto1GHzoutputfrequencies.PECLoutputs.PECLreferenceclock.32-pinTQFPpackage.

ReplacementforMotorola®MPC998withPECLinputsandoutputs.

LCK4802hasthesameexpandedfrequency

rangeandimprovedperformanceastheLCK4801butwithPECLinputsandoutputs:

—MPC998rangeis520MHz—840MHz.—LCK4802rangeis336MHz—1GHz.

s

Description

PCLK0_EN(PULL-UP)PCLK1_EN(PULL-UP)

TESTM(PULL-UP)PLLREF_EN(PULL-UP)REF_SEL(PULL-UP)PECL_CLK(PULL-UP)PECL_CLK(PULL-UP)PECL_CLK(PULL-UP)PECL_CLK(PULL-UP)(PULL-UP)

EXTFB_IN(PECL)

(PULL-DOWN)

EXTFB_EN(PULL-UP)

EXTFB_OUT(PECL)

SEL[4:0](PULL-UP)RESET(PULL-UP)

PLL_BYPASS(PULL-UP)

2274.b(F)

10

01

01/N

EXTFB_OUT

/M

PLL

01

PCLK0PCLK0(PECL)PCLK1PCLK1(PECL)

DECODE

Figure1.LCK4802LogicDiagram

LCK4802

Low-VoltagePECLDifferentialClockAdvanceDataSheet

December2001

Description(continued)

2SSNAEP_YFLLBEC0011C_REKKKKELLPLLLLPLLDDCCCCDDPPVPPPPVV232221201918

17SS252416EXTFB_OUTRESET2615EXTFB_OUTSEL[4]2714VDDPECLSEL[3]2813EXTFB_INSEL[2]2912EXTFB_INSEL[1]3011EXTFB_ENSEL[0]3110

PECL_CLKVDDA

32123456789

PECL_CLK

DDMSNNLKKDTSEEELLVSV__SCCE01___TKKFLLLLECCCCREEPPPPFigure2.32-PinTQFP

2275(F)

AgereSystemsInc.

AdvanceDataSheetDecember2001LCK4802

Low-VoltagePECLDifferentialClock

PinInformation

Table1.PinDescriptionPinNumber

1234567891011121314151617181920212223242526272829303132

PinNameVDDDTESTMVSSPCLK0_ENPCLK1_ENREF_SELPECL_CLKPECL_CLKPECL_CLKPECL_CLKEXTFB_ENEXTFB_INEXTFB_INVDDPECLEXTFB_OUTEXTFB_OUTVDDPECLPCLK1PCLK1PCLK0PCLK0VDDPECLPLLREF_ENPLL_BYPASS

VSSRESETSEL[4]SEL[3]SEL[2]SEL[1]SEL[0]VDDA

I/O1PIGIIIIIIIIIIPOOPOOOOPIIPIIIIIIP

TypePowerSupplyLVCMOSGroundLVCMOSLVCMOSLVCMOSDifferentialPECLDifferentialPECL

Description

3.3Vpowersupply.Mdividertestpins.Digitalground.PCLK0enable.PCLK1enable.

SelectsthePLLinputreferenceclock.PLLreferenceclockinput.PLLreferenceclockinput.

DifferentialLVPECLPLLreferenceclockinput.DifferentialLVPECLPLLreferenceclockinput.

LVCMOSDifferentialPECLDifferentialPECLPowerSupplyDifferentialPECLDifferentialPECLPowerSupplyDifferentialPECLDifferentialPECLDifferentialPECLDifferentialPECLPowerSupplyLVCMOSLVCMOSGroundLVCMOSLVCMOSLVCMOSLVCMOSLVCMOSLVCMOSPowerSupply

Externalfeedbackenable.Externalfeedbackinput.Externalfeedbackinput.Outputbufferspowersupply.Externalfeedbackoutputclock.Externalfeedbackoutputclock.Outputbufferspowersupply.Outputclock1.Outputclock1.Outputclock0.Outputclock0.

Outputbufferspowersupply.PLLreferenceenable.InputsignalPLLbypass.AnaloggroundforPLL.PLLbypassreset(fortestuse).

Selectionofinputandfeedbackfrequency.Selectionofinputandfeedbackfrequency.Selectionofinputandfeedbackfrequency.Selectionofinputandfeedbackfrequency.Selectionofinputandfeedbackfrequency.3.3VfilteredforPLL(PLLpowersupply).

1.P=power,I=input,G=ground,O=output.

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LCK4802

Low-VoltagePECLDifferentialClockAdvanceDataSheet

December2001

PinInformation(continued)

Table2.FrequencySelection

Selection

400000000000000001111111111111111

300000000111111110000000011111111

200001111000011110000111100001111

100110011001100110011001100110011

001010101010101010101010101010101

InputDivideM55555555555555555555555555555555

FeedbackDivide

N2425262728293031323334353637383940414243444546474849505152535455

PCLK(MHz)

forGivenInputFrequency(MHz)70336350364378392406420434448462476490504518532546560564588602616630644658672686700714728742756770

1004805005205405605806006206406606807007207407607808008208408608809009209409609801000NANANANANA

120576600624648672696720744768792816840864888912936960984NANANANANANANANANANANANANANA

1256006256506757007257507758008258508759009259509751000NANANANANANANANANANANANANANANA

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AdvanceDataSheetDecember2001LCK4802

Low-VoltagePECLDifferentialClock

PinInformation(continued)

Table3.FunctionControl

ControlPinREF_SELTESTMPLLREF_ENPLL_BYPASSEXTFB_ENPCLK0_ENPCLK1_ENRESETSEL[4:0]

PECL_CLK.

Mdividertestmodeenabled.DisabletheinputtothePLLandresettheMdivider.

OutputsfedbyinputreferenceorMdivider.

Externalfeedbackenabled.PCLK0=low,PCLK0=high.PCLK1=low,PCLK1=high.ResetsfeedbackNdivider.SeeTable2onpage4.

0

PECL_CLK.

ReferencefedtobypassMUX.EnabletheinputtothePLL.OutputsfedbyVCO.Internalfeedbackenabled.PCLK0=high,PCLK0=low.PCLK1=high,PCLK1=low.Feedbackenabled.SeeTable2onpage4.

1

AbsoluteMaximumCharacteristics

Stressesinexcessoftheabsolutemaximumratingscancausepermanentdamagetothedevice.Theseareabsolutestressratingsonly.Functionaloperationofthedeviceisnotimpliedattheseoranyotherconditionsinexcessofthosegivenintheoperationalsectionsofthedatasheet.Exposuretoabsolutemaximumratingsforextendedperiodscanadverselyaffectdevicereliability.Table4.AbsoluteMaximumRatings

ParameterPowerSupplyInputVoltageWriteCurrent

StorageTemperature

SymbolVDDD/VDDAVDDPECL

VINIINTS

Min–0.5–0.5–0.5–1–50

Typical—————

Max4.44.4VDDD+0.3

1150

UnitVVmA°C

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LCK4802

Low-VoltagePECLDifferentialClockAdvanceDataSheet

December2001

ElectricalCharacteristics

Table5.dcCharacteristics

VDDA=VDDD=3.3V±5%,VDDPECL=1.7V—2.1V,TA=0°C—70°C.

SymbolVIHVILVCMRVPPVOHVOLIDDIIDDAIDDOThetaJA

DescriptionInputHighVoltageInputLowVoltageInputHighVoltage1InputLowVoltage1OutputHighVoltageOutputLowVoltageCoreSupplyCurrentPLLSupplyCurrentOutputSupplyCurrentJunctiontoAmbientThermalResistance

Min2.21.5VDDD–1.3

0.52.01.3————

Typ———————1515053

Max2.41.8VDDD–0.5

—2.61.914020——

UnitVVVVVVmAmAmA°C/W

ConditionLVCMOSLVCMOSLVPECLLVPECLPECLPECL———2—31.dclevelswillvary1:1withVDDD.

2.TwoPCLKsignalsto25Ω,andoneEXTFBsignalthrough50Ω.3.1.3M/s(250fpm)airflow.

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AdvanceDataSheetDecember2001LCK4802

Low-VoltagePECLDifferentialClock

ElectricalCharacteristics(continued)Table6.acCharacteristicsVDDA=VDDD=3.3V±5%,VDDPECL=1.7V—2.1V,TA=0°C—70°C.SymbolfreffMAXtsk(o)tjit(0)tjit(cc)DescriptionInputFrequencyMaximumOutputFrequencySkewError(PCLK)PhaseJitter(I/OJitter)Cycle-to-CycleJitter(FullPeriod)Min—336————0.60.68—Typ70—125————————Max—100035(outputperiod)/258—0.910UnitMHzMHZps—%%VVmsCondition——1—2—2—2,3—2,4ForallPECLoutputpairs.ForallPECLoutputpairs.—tjit(1/2period)Cycle-to-CycleJitter(HalfPeriod)VDIFoutVXtlockDifferentialOutputPeak-to-PeakSwingDifferentialOutputCrosspointVoltageMaximumPLLLockTime1.Whenthephase-lockedloopisactivebutinbypassmode,frefmaximumislimitedbyinputthebuffer;optimumperformanceisobtainedfromPECLinput.2.Atdifferentialpaircrossover.3.FullPCLKperiod.4.HalfPCLKperiod.VDDPECLVOHVDIFVXVCMVOLVSS2276(F)Figure3.PECLDifferentialInputLevelsZ=50ΩOUTPUTRT=25ΩVTT=VSS(GROUND)2277.a(F)Figure4.OutputTerminationandacTestReferenceAgereSystemsInc.7LCK4802

Low-VoltagePECLDifferentialClockAdvanceDataSheet

December2001

Applications

PowerSupplyFiltering

TheLCK4802isamixedanalog/digitalproduct.Becauseofthis,itexhibitssomesensitivitiesthatwouldnot

necessarilybeseenonafullydigitalproduct.Analogcircuitryissusceptibletorandomnoise,theworstcasebeingwhenthisnoiseisseenonthepowersupplypins.TheLCK4802providesseparatepowersuppliesfortheoutputbuffers(VDDPECL)andthephase-lockedloop(VDDA)ofthedeviceinordertoisolatethehighdigitaloutput

switchingnoisefromtheinternalanalogPLL.Inacontrolledevaluationboardenvironment,thislevelofisolationisadequate.However,inadigitalsystem,asecondlevelofisolationissuggested.

TheeasiestwaytoaccomplishthisistoaddapowersupplyfilterontheVDDApinoftheLCK4802.Figure5onpage9showsthetypicalpowersupplyscheme.Thefiltershouldbedesignedinthe10kHz—1MHzrange,sincethisisthemostlikelyfrequencyrangetocausespectralcontentnoise.

NotethedcvoltagedropbetweenVDDDandVDDAonthepowersupplyfilter.Verylittledcvoltagedropcanbetoleratedwhena3.3VVDDDsupplyisused.ThepowersupplyfilterinFigure5mustbe5Ω—10Ωinordertomeetthedropcriteria.TheRCfilterinFigure5willprovideabroadbandfilterwithapproximately100:1attenuationabove20kHz.

Theimpedanceofanindividualcapacitorbeginstoappearinductiveandincreaseswithfrequencyasthenoisefrequencycrossestheseriesresonantpointofthecapacitor.TheparallelcapacitorcombinationensuresthatforfrequenciesmuchgreaterthanthebandwidthofthePLLthereisalwaysalow-impedancepath.

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AdvanceDataSheetDecember2001LCK4802

Low-VoltagePECLDifferentialClock

Applications(continued)

3.3V

RS=5—10Ω

VDDA

0.01µF

22µF

VDDD

0.01µF

2278(F)

Figure5.PowerSupplyFilter

AlthoughtheLCK4802hasanisolatedpowersupplyandgrounds,aswellasfullydifferentialPLL,therestillmaybeapplicationsinwhichoverallperformanceisbeingcompromisedduetosystempowersupplynoise.Thepowersupplyfilterschemesdiscussedareadequatetoeliminatepowersupplynoiseproblemsinmostdesigns.

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LCK4802

Low-VoltagePECLDifferentialClockAdvanceDataSheet

December2001

OutlineDiagram

Dimensionsareinmillimeters.

9.00±0.207.00±0.20PIN#1IDENTIFIERZONE32251.00REF

0.25

GAGEPLANE

1

24SEATINGPLANE

0.45/0.75

7.00±0.209.00±0.20DETAILA

8179160.09/0.200

DETAILA

DETAILB

1.40±0.05

0.30/0.45

0.20

M1.60MAXSEATINGPLANE

0.100.80TYP

0.05/0.15

DETAILB

12-3076(F)

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December2001

DS02-070HSI(ReplacesDS01-265HSI)